migen安装与使用

尝试用Migen编写FPGA的逻辑，文章记录下来migen的安装与使用

Migen is a Python-based tool that automates further the VLSI design process.

安装

安装python环境

python3.6.8

安装migen包

pip install migen

安装 Icarus Verilog 和GTKwave

Iverilog下载地址：

Icarus Verilog for Windows (bleyer.org) (opens new window)

环境测试

官网上的例程更新太慢（不好使了），参考库里的例程

from migen import *


# Our simple counter, which increments at every cycle.
class Counter(Module):
    def __init__(self):
        self.count = Signal(4)

        # At each cycle, increase the value of the count signal.
        # We do it with convertible/synthesizable FHDL code.
        self.sync += self.count.eq(self.count + 1)


# Simply read the count signal and print it.
# The output is:
# Count: 0
# Count: 1
# Count: 2
# ...
def counter_test(dut):
    for i in range(20):
        print((yield dut.count))  # read and print
        yield  # next clock cycle
    # simulation ends with this generator


if __name__ == "__main__":
    dut = Counter()
    run_simulation(dut, counter_test(dut), vcd_name="basic1.vcd")

运行成功后会在目录下生成 basic1.vcd，

用gtkwave可以查看波形了

编译文档

1、clone代码

https://github.com/m-labs/migen.git

2、python 安装库

pip install -U sphinx

pip install sphinx_rtd_theme

3、打开命令终端，到代码的 migen\doc 目录下,执行编译命令

sphinx-build -b html . build

则会在build中生成migen文档